Aug 18, 2026 – New Taipei City, Taiwan – As artificial intelligence (AI), high-performance computing (HPC), GPUs, and various AI accelerators continue to advance toward higher compute density, larger transient currents, and lower core operating voltages, the power integrity challenges faced by the Power Delivery Network (PDN) are becoming increasingly severe. To address voltage droop, power noise, and transient fluctuations caused by rapid load changes in processors, Zowie Technology is developing ultra-thin multilayer polymer aluminum electrolytic capacitors (MLPC) for embedded applications. Through design features including thinning, low ESR, double-sided terminal electrodes, and low-stress packaging, Zowie Technology aims to evolve capacitors from conventional surface-mount devices into embedded power integrity solutions for AI/HPC platforms.

Y.P. Chung, Chairman of Zowie Technology, stated that when a large number of computing units in high-performance processors switch simultaneously, load current can increase dramatically in an extremely short time. The voltage regulator module (VRM) cannot supply the full additional current instantaneously and must be supported first by decoupling capacitors located close to the load. If capacitors are placed too far from the processor, even with sufficient nominal capacitance, the current must still pass through pads, traces, vias, power/ground planes, and package interconnects—parasitic resistance and inductance may still limit transient response. Therefore, what AI power architectures truly need to solve is not merely increasing capacitance, but rather placing sufficient effective capacitance at a sufficiently low impedance as close to the load as possible.

Item	7343Ultra-ThinMLPC	3528CompactMLPC
Dimensions	Approx. 7.3 × 4.3 mm	Approx. 3.5 × 2.8 mm
Target Thickness	0.6～0.8 mm	0.6～0.8 mm
Capacitance Range	Approx. 140～220 µF	Approx. 50 µF
Target ESR	Approx. 4.5～6 mΩ	To be verified based on the final structure
Primary Positioning	High-Capacitance Local Decoupling	Distributed Embedded Decoupling

Table 1. Development roadmap for ZOWIE Technology’s ultra-thin MLPC product platform. The actual capacitance and ESR values remain subject to confirmation based on the capacitor core structure, rated voltage, and final measurement conditions.

Figure 1. Schematic illustration of the double-sided electrode MLPC structure developed by ZOWIE Technology. Both the top and bottom surfaces feature terminal electrodes, which can work with the upper and lower conductive layers of an embedded substrate and microvias to form shorter vertical conductionpaths.

Traditional power supply designs for AI GPUs and high-power ASICs typically employ large numbers of multilayer ceramic capacitors (MLCC) and polymer capacitors to cover decoupling needs across different frequency ranges. Larger bulk polymer capacitors located farther away handle low-frequency energy storage, capacitors near the GPU handle mid-to-low frequency transient currents, and low-ESL MLCCs closest to the chip or package power terminals handle high-frequency and ultra-high-frequency noise. However, as available board area shrinks, competition among surface-mount component count, component height, routing, thermal dissipation space, and package interconnects becomes increasingly pronounced. Simply increasing the number of surface-mount capacitors can no longer deliver proportional performance improvements.

Figure 2. Conceptual diagram comparing the traditional architecture with the future embedded hybrid architecture.

Zowie Technology’s ultra-thin MLPC is built around the core concept of “Design for Embedding,” simultaneously considering thickness, capacitance, ESR, terminal electrode structure, packaging materials, and embedded manufacturing requirements from the product design stage. The current product platform includes two form factors: 7343 and 3528. The 7343 package measures approximately 7.3×4.3 mm, with a target thickness of 0.6 to 0.8 mm. Capacitance can range from approximately 140 µF to 220 µF, depending on the number of stacked elements and layering configuration. The primary ESR development target is 4.5 to 6 mΩ, positioning it as a high-capacitance local decoupling product. The 3528 package measures approximately 3.5×2.8 mm, with the same 0.6 to 0.8 mm thickness target and capacitance of approximately 50 µF, focusing on miniaturization and distributed embedded decoupling applications.

En-Ming Chen, Special Assistant to the President of Zowie Technology, pointed out that the 0.6 mm and 0.8 mm thickness options correspond to different engineering trade-offs. The 0.6 mm product serves embedded spaces with extremely tight Z-height constraints, while the 0.8 mm product can potentially achieve higher capacitance or lower ESR by increasing the number of stacked elements, forming a high-performance series. For PDN applications, the optimization goal is not to pursue the thinnest possible design, but rather to deliver higher power delivery capability within an acceptable thickness range. If increasing thickness by approximately 0.2 mm can boost capacitance from roughly 140 µF to over 200 µF while maintaining 5 mΩ-class ESR, the system value may exceed that of a product that merely pursues extreme thinning.

The double-sided terminal electrode is a key structural feature of Zowie Technology’s ultra-thin MLPC. Conventional surface-mount polymer aluminum capacitors primarily connect through bottom electrodes to PCB surface pads. When components are embedded inside the PCB or substrate, if copper foil must still be drawn from the side edges and connected to Power/Ground layers through vias, the electrical advantages that embedded components could potentially offer may be limited. Double-sided terminal electrodes enable electrical connections on both the top and bottom of the component—the top surface can connect via microvias to the upper Power Layer, while the bottom surface connects to the lower Ground Layer, allowing current to follow a shorter vertical path along the Z-direction.

Y.P. Chung stated that the value of double-sided electrodes is not merely “one more connection surface,” but rather enabling the capacitor structure to participate in three-dimensional power network design. When MLPCs are placed directly between Power and Ground layers with short connections established through top and bottom terminal electrodes, designers can simultaneously optimize component placement, conductor planes, and power delivery paths, reducing the total loop inductance contributed collectively by components, terminal electrodes, vias, planes, and packaging.

In terms of application architecture, Zowie Technology emphasizes that ultra-thin MLPCs are not intended to fully replace MLCCs, but rather to form a hybrid decoupling architecture together with low-ESL high-frequency MLCCs. Future systems can gradually evolve from “surface bulk capacitors plus large-scale MLCC arrays” to “surface bulk capacitors plus embedded MLPCs plus high-frequency MLCCs.” In this architecture, embedded MLPCs handle larger local effective capacitance and mid-to-low frequency transient support, while high-frequency MLCCs continue to leverage their advantages in high-frequency and ultra-high-frequency decoupling. By moving some high-capacitance decoupling functions from the PCB surface into the substrate, systems have the opportunity to reduce the number of certain large-capacitance MLCCs, free up surface area around the GPU, shorten current loops, and improve power delivery density.

The focus of this strategy is not to establish a fixed “one MLPC replaces X number of MLCCs” relationship, but rather to find the optimal combination of “Embedded MLPC plus Reduced MLCC” through PDN simulation and actual testing. Different MLCCs vary in capacitance, packaging, DC bias characteristics, ESR, ESL, and placement location, so the actual replacement count must be verified against system metrics such as target impedance, voltage droop, and load transient response. Zowie Technology believes that thin MLPCs are better suited for the region between bulk and mid-frequency decoupling, while the high-frequency MLCCs closest to the processor should still be retained, achieving a rational division of labor among different capacitors in both frequency and spatial domains.

The 7343 and 3528 products also correspond respectively to centralized and distributed PDN strategies. The 7343, with approximately 140 to 220 µF capacitance, can be used in localized power regions of GPUs or AI ASICs, providing substantial energy storage and local decoupling capability. The 3528, with approximately 50 µF, is suitable for distributed placement near different Power Rails or load hotspots. Taking four 50 µF products as an example, the nominal total capacitance is approximately 200 µF, but the value of distributed placement is not equivalent to a single 200 µF capacitor, because multiple smaller components can be placed closer to different load regions, shortening each one’s power delivery distance and improving placement efficiency.

For embedded components, beyond electrical performance, thermo-mechanical reliability is equally critical for successful volume production. After being encapsulated by resin, prepreg, and copper layers, the component forms a tighter composite material system with the substrate. During lamination, reflow soldering, temperature cycling, power cycling, and long-term high-temperature operation, differences in the coefficient of thermal expansion (CTE) among different materials may translate into interfacial stress, concentrating at terminal electrodes, package boundaries, microvia connection regions, resin interfaces, or internal elements.

Therefore, Zowie Technology has incorporated low mechanical stress and substrate-CTE-matched material design direction from the packaging stage, aiming to reduce interfacial stress risks caused by thermal expansion mismatch after embedding. Subsequent reliability verification will cover TMA CTE measurement, temperature cycling, high-temperature storage, lamination tolerance, moisture absorption and reflow, microvia connection reliability, and cross-section and failure analysis. The company states that only when material matching design and accelerated life data corroborate each other can the low-stress packaging product concept be further translated into reliability evidence that customers can trust.

Targeting the AI/HPC market, Zowie Technology extends the future competitive metric from simple “capacitance density” to “power delivery density.” For embedded applications, the highest capacitance does not necessarily represent the best product. If increasing capacitance requires a significant thickness increase that prevents the capacitor from being placed in critical locations, a higher microfarad rating may lose its system value. In comparison, a 220 µF, 0.8 mm thick, low-ESR MLPC that can be placed exactly where the GPU truly needs it may offer greater value than a higher-capacitance component that can only be placed farther away.

To drive the product from a component toward an Embedded Power Integrity Solution, Zowie Technology has planned four levels of development and verification pathways. Level 1 covers electrical characteristics, including capacitance, ESR, ESL, impedance-frequency curves, leakage current, and temperature characteristics. Level 2 covers materials and packaging, including CTE, glass transition temperature, mechanical properties, and moisture absorption. Level 3 covers the embedded manufacturing process, including cavity tolerances, component deformation after lamination, resin filling, laser drilling, via-to-electrode alignment, copper plating, and cross-section integrity. Level 4 covers system-level PDN verification, using test vehicles or GPU/ASIC emulation boards to compare the performance of pure MLCC architectures versus hybrid MLPC-plus-MLCC architectures in terms of load transient response, voltage drop, and impedance profiles, while quantifying the number of MLCCs that can be reduced and the surface area that can be freed.

Y.P. Chung concluded that the first two technical tiers are now approaching maturity, while subsequent embedded manufacturing and system PDN verification will require cross-industry collaboration with substrate, packaging, and system manufacturers. As relevant process, reliability, and system performance data are gradually established, the ultra-thin double-sided electrode MLPC is expected to evolve from a novel passive component into an embedded power integrity solution that is easier to integrate into customer design flows and backed by system-level verification.

Against the backdrop of AI GPUs, AI ASICs, and HPC systems continuously increasing current density, thermal density, and layout density, the future value of capacitors will no longer be determined solely by nominal capacitance or single-parameter ESR, but rather by the ability to deliver effective, low-impedance power support within limited volume, thickness, and distance. Through its 0.6-to-0.8 mm ultra-thin platform, 7343 and 3528 product portfolio, 4.5-to-6 mΩ low-ESR targets, double-sided terminal electrodes, and low-stress packaging design, Zowie Technology is working to advance power delivery from two-dimensional surface configuration toward three-dimensional layered integration, offering new power design pathways for next-generation high-density AI/HPC platforms.

About Zowie

ZOWIE Technology Corporation founded in1994 isa leading designer andmanufacturer of advanceddiscrete semiconductor products.Theinaugurators, Ding-Hua Hu and George Tai are the well-known leaders in the semiconductor field in Taiwan. Since there is no new significant progress in diode products for more than 20 years they decided to endeavor their efforts to this industry with innovation and futurity.

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Company Name: Zowie Technology Corporation
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Website: http://www.zowie.com.tw